1. Field of the Invention
The present invention generally relates to a reset circuit and a control apparatus including the reset circuit.
2. Description of the Related Art
As one related art example, there is known a power-on reset circuit that terminates outputting of a reset signal when the voltage of a power source is detected to exceed a predetermined threshold. As one example of the power-on reset circuit, FIG. 1 illustrates a reset circuit 1 having an open drain output. In a case of the reset circuit 1, a comparator C1 outputs a high level gate drive signal VG when a divided voltage Vc (obtained by dividing a power supply voltage VDD with resistors R1, R2, and R3) is lower than a reference voltage Vref. Accordingly, because the reset circuit 1 switches on a transistor N0 by outputting the high level gate drive signal VG, the reset circuit 1 switches the voltage level POR of an output terminal 13 to a low level. On the other hand, the reset circuit 1 outputs a low level gate drive signal VG when the divided voltage Vc is higher than the reference voltage Vref. Accordingly, because the reset circuit 1 switches off the transistor N0 by outputting the low level gate drive signal VG, the reset circuit 1 switches the voltage level POR of the output terminal 13 to a high level.
In other words, in the case of the reset circuit 1 illustrated in FIG. 1, the voltage level POR is switched to a low level when the status of the voltage of the power source (power supply voltage) VDD becomes a low voltage state that requires an external apparatus (not illustrated) to be reset, and the voltage level POR is switched to a high level when the status of the voltage of the power supply voltage VDD becomes a steady voltage state that allows the resetting of the external apparatus to be terminated.
For example, Japanese Laid-Open Patent Publication No. 2001-141761 discloses a reset circuit according to a related art example.
With the reset circuit illustrated in FIG. 1, the comparator C1, which uses the power supply voltage VDD as a power source for operation, is unable to output a voltage sufficient to switch on the transistor N0 when the power supply voltage VDD is in an ultra-low voltage state being slightly larger than 0 (zero) V. Thus, because the transistor N0 is unable to acquire electric current, the voltage level POR of the output terminal 13 becomes a high level.
In recent years, however, the operating voltage (voltage for operating) of control circuits (e.g., microcomputers) is becoming lower. Therefore, even if the power supply voltage VDD is in the ultra-low voltage state where the resetting of the power source voltage should not be allowed, a control circuit may determine that the resetting is terminated when the voltage level POR becomes a high level.
Because the circuit disclosed in Japanese Laid-Open Patent Publication No. 2001-141761 is used for a case of CMOS output, the circuit of Japanese Laid-Open Patent Publication No. 2001-141761, being capable of switching the voltage of an output terminal even where the power supply voltage VDD is in the ultra-low voltage state, cannot be applied to the reset circuit 1 of FIG. 1 having the open drain output.